Conventionally, in the process of producing a semiconductor device such as IC and LSI, a number of IC chips are usually formed on a semiconductor silicon wafer and individualized by dicing.
In response to needs for more size reduction and higher performance of an electronic device, the IC chip mounted in an electronic device is also required to satisfy more size reduction and higher density packaging, but the high density packaging of integrated circuits in the surface direction of a silicon substrate is reaching the near limit.
As to the method for establishing an electrical connection from an integrated circuit within an IC chip to an external terminal of the IC chip, a wire bonding method has been heretofore widely known, but in order to realize size reduction of an IC chip, a method of providing a through hole in a silicon substrate so that a metal plug as an external terminal can be passed through the through hole and thereby connected to an integrated circuit (a method of forming a so-called through-silicon via (TSV)) is recently known. However, only with the method of forming a through-silicon via, the recent needs for higher density packaging in an IC chip cannot be sufficiently responded.
In consideration of these things, a technique of fabricating multilayer integrated circuits within an IC chip and thereby increasing the integration degree per unit area of a silicon substrate is known. However, fabrication of multilayer integrated circuits increases the thickness of the IC chip, and thinning of a member constituting the IC chip is required. As to such thinning of a member, for example, thinning of a silicon substrate is being studied and this not only leads to size reduction of an IC chip but also enables labor saving in the step of forming a through hole in a silicon substrate at the production of a through-silicon via and therefore, is promising.
A wafer having a thickness of approximately from 700 to 900 μm is widely known as the semiconductor silicon wafer used in the process of producing a semiconductor device, but in recent years, for the purpose of achieving, for example, size reduction of an IC chip, an attempt is being made to reduce the thickness of the semiconductor silicon wafer to 200 μm or less.
However, the semiconductor silicon wafer having a thickness of 200 μm or less is very thin and in turn, a member for the production of a semiconductor device, which uses this wafer as the base material, is very thin, making it difficult to stably support the member without a damage, for example, when applying a further treatment to the member or merely moving the member.
In order to solve such a problem, there is known a technique of temporarily adhering an unthinned semiconductor wafer having provided on the surface a device to a supporting substrate for processing with a pressure-sensitive adhesive, grinding the back surface of the semiconductor wafer to achieve thinning, perforating the semiconductor wafer, providing a through-silicon via, and thereafter detaching the supporting substrate for processing from the semiconductor wafer (see, JP-A-2011-119427 (the term “JP-A” as used herein means an “unexamined published Japanese patent application”)). It suggested that according to this technique, all of grinding resistance at the back surface grinding of semiconductor wafer, heat resistance in an anisotropic dry etching step or the like, chemical resistance at the plating or etching, smooth separation from the final supporting substrate for processing, and low contamination for adherend can be satisfied at the same time.
As to the method for supporting a wafer, there is known a method of supporting a wafer by a supporting layer system, where a plasma polymer layer obtained by a plasma deposition method is caused to intervene as a separating layer between the wafer and the supporting layer and the adhesive bonding between the supporting layer system and the separating layer is larger than the joint bonding between the wafer and the separating layer to allow for easy detachment of the wafer from the separating layer when detaching the wafer from the supporting layer system (see, JP-T-2009-528688 (the term “JP-T” as used herein means a published Japanese translation of a PCT patent application)).